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? semiconductor components industries, llc, 2001 january, 2001 rev. 3 1 publication order number: dtc114eet1/d dtc114eet1 series bias resistor transistor npn silicon surface mount transistor with monolithic bias resistor network this new series of digital transistors is designed to replace a single device and its external resistor bias network. the brt (bias resistor transistor) contains a single transistor with a monolithic bias network consisting of two resistors; a series base resistor and a baseemitter resistor. the brt eliminates these individual components by integrating them into a single device. the use of a brt can reduce both system cost and board space. the device is housed in the sc75/sot416 package which is designed for low power surface mount applications. ? simplifies circuit design ? reduces board space ? reduces component count ? the sc75/sot416 package can be soldered using wave or reflow. the modified gullwinged leads absorb thermal stress during soldering eliminating the possibility of damage to the die. ? available in 8 mm, 7 inch/3000 unit tape & reel maximum ratings (t a = 25 c unless otherwise noted) rating symbol value unit collector-base voltage v cbo 50 vdc collector-emitter voltage v ceo 50 vdc collector current i c 100 madc http://onsemi.com npn silicon bias resistor transistors sc75/sot416 case 463 style 1 3 2 1 pin 3 collector (output) pin 2 emitter (ground) pin 1 base (input) r1 r2 8x = specific device code x = (see marking table on page 2) m = date code marking diagram 8x m
dtc114eet1 series http://onsemi.com 2 device marking and resistor values device marking r1 (k) r2 (k) shipping dtc114eet1 dtc124eet1 dtc144eet1 dtc114yet1 dtc114tet1 dtc143tet1 dtc123eet1 dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 dtc115eet1 dtc144wet1 8a 8b 8c 8d 8e 8f 8h 8j 8k 8l 8m 8n 8p 10 22 47 10 10 4.7 2.2 4.7 4.7 22 2.2 100 47 10 22 47 47 2.2 4.7 47 47 47 100 22 3000/tape & reel thermal characteristics characteristic symbol max unit total device dissipation, fr4 board (note 1.) @ t a = 25 c derate above 25 c p d 200 1.6 mw mw/ c thermal resistance, junction to ambient (note 1.) r q ja 600 c/w total device dissipation, fr4 board (note 2.) @ t a = 25 c derate above 25 c p d 300 2.4 mw mw/ c thermal resistance, junction to ambient (note 2.) r q ja 400 c/w junction and storage temperature range t j , t stg 55 to +150 c 1. fr4 @ minimum pad 2. fr4 @ 1.0 1.0 inch pad
dtc114eet1 series http://onsemi.com 3 electrical characteristics (t a = 25 c unless otherwise noted) characteristic symbol min typ max unit off characteristics collectorbase cutoff current (v cb = 50 v, i e = 0) i cbo 100 nadc collectoremitter cutoff current (v ce = 50 v, i b = 0) i ceo 500 nadc emitterbase cutoff current dtc114eet1 (v eb = 6.0 v, i c = 0) dtc124eet1 dtc144eet1 dtc114yet1 dtc114tet1 dtc143tet1 dtc123eet1 dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 dtc115eet1 dtc144wet1 i ebo 0.5 0.2 0.1 0.2 0.9 1.9 2.3 1.5 0.18 0.13 0.2 0.05 0.13 madc collectorbase breakdown voltage (i c = 10 m a, i e = 0) v (br)cbo 50 vdc collectoremitter breakdown voltage (note 3.) (i c = 2.0 ma, i b = 0) v (br)ceo 50 vdc on characteristics (note 3.) dc current gain dtc114eet1 (v ce = 10 v, i c = 5.0 ma) dtc124eet1 dtc144eet1 dtc114yet1 dtc114tet1 dtc143tet1 dtc123eet1 dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 dtc115eet1 dtc144wet1 h fe 35 60 80 80 160 160 8.0 15 80 80 80 80 80 60 100 140 140 350 350 15 30 200 150 140 150 140 collectoremitter saturation voltage (i c = 10 ma, i b = 0.3 ma) (i c = 10 ma, i b = 5 ma) dtc123eet1 (i c = 10 ma, i b = 1 ma) dtc143tet1/dtc114tet1/ dtc143eet1/dtc143zet1/dtc124xet1 v ce(sat) 0.25 vdc output voltage (on) (v cc = 5.0 v, v b = 2.5 v, r l = 1.0 k w ) dtc114eet1 dtc124eet1 dtc114yet1 dtc114tet1 dtc143tet1 dtc123eet1 dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 (v cc = 5.0 v, v b = 3.5 v, r l = 1.0 k w ) dtc144eet1 (v cc = 5.0 v, v b = 5.5 v, r l = 1.0 k w ) dtc115eet1 (v cc = 5.0 v, v b = 4.0 v, r l = 1.0 k w ) dtc144wet1 v ol 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.2 vdc output voltage (off) (v cc = 5.0 v, v b = 0.5 v, r l = 1.0 k w ) (v cc = 5.0 v, v b = 0.25 v, r l = 1.0 k w ) dtc143tet1 dtc143zet1 dtc114tet1 v oh 4.9 vdc 3. pulse test: pulse width < 300 m s, duty cycle < 2.0%
dtc114eet1 series http://onsemi.com 4 electrical characteristics (t a = 25 c unless otherwise noted) (continued) characteristic symbol min typ max unit input resistor dtc114eet1 dtc124eet1 dtc144eet1 dtc114yet1 dtc114tet1 dtc143tet1 dtc123eet1 dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 dtc115eet1 dtc144wet1 r1 7.0 15.4 32.9 7.0 7.0 3.3 1.5 3.3 3.3 15.4 1.54 70 32.9 10 22 47 10 10 4.7 2.2 4.7 4.7 22 2.2 100 47 13 28.6 61.1 13 13 6.1 2.9 6.1 6.1 28.6 2.86 130 61.1 k w resistor ratio dtc114eet1/dtc124eet1/dtc144eet1/ dtc115eet1 dtc114yet1 dtc143tet1/dtc114tet1 dtc123eet1/dtc143eet1 dtc143zet1 dtc124xet1 dtc123jet1 dtc144wet1 r 1 /r 2 0.8 0.17 0.8 0.055 0.38 0.038 1.7 1.0 0.21 1.0 0.1 0.47 0.047 2.1 1.2 0.25 1.2 0.185 0.56 0.056 2.6 figure 1. derating curve 250 200 150 100 50 0 -50 0 50 100 150 t a , ambient temperature ( c) p d , power dissipation (milliwatts) r q ja = 600 c/w 0.00001 0.0001 0.001 0.01 0.1 1.0 10 100 1000 0.001 0.01 0.1 1.0 r(t), normalized transient thermal resistance t, time (s) single pulse 0.01 0.02 0.05 0.1 0.2 d = 0.5 figure 2. normalized thermal response
dtc114eet1 series http://onsemi.com 5 typical electrical characteristics dtc114eet1 v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain (normalized) figure 3. v ce(sat) versus i c 10 02030 i c , collector current (ma) 10 1 0.1 t a =-25 c 75 c 25 c 40 50 figure 4. dc current gain figure 5. output capacitance 1 0.1 0.01 0.001 020 40 50 i c , collector current (ma) v ce(sat) , maximum collector voltage (volts) 1000 100 10 1 10 100 i c , collector current (ma) t a =75 c 25 c -25 c t a =-25 c 25 c figure 6. output current versus input voltage 75 c 25 c t a =-25 c 100 10 1 0.1 0.01 0.001 01 234 v in , input voltage (volts) 56 78 910 figure 7. input voltage versus output current 50 010203040 4 3 1 2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) 75 c v ce = 10 v f = 1 mhz i e = 0 v t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10
dtc114eet1 series http://onsemi.com 6 typical electrical characteristics dtc124eet1 v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain (normalized) figure 8. v ce(sat) versus i c figure 9. dc current gain figure 10. output capacitance figure 11. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 10 1 100 75 c 25 c 100 0 v in , input voltage (volts) 10 1 0.1 0.01 0.001 246810 t a =-25 c 0 i c , collector current (ma) 100 t a =-25 c 75 c 10 1 0.1 10 20 30 40 50 25 c figure 12. input voltage versus output current 0.001 v ce(sat) , maximum collector voltage (volts ) t a =-25 c 75 c 25 c 0.01 0.1 1 40 i c , collector current (ma) 0 20 50 50 0 10 203040 4 3 2 1 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) i c /i b = 10 v ce = 10 v f = 1 mhz i e = 0 v t a = 25 c v o = 5 v v o = 0.2 v
dtc114eet1 series http://onsemi.com 7 typical electrical characteristics dtc144eet1 v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain (normalized) figure 13. v ce(sat) versus i c 0246810 100 10 1 0.1 0.01 0.001 v in , input voltage (volts) t a =-25 c 75 c 25 c figure 14. dc current gain figure 15. output capacitance 100 10 1 0.1 010 20 3040 50 i c , collector current (ma) figure 16. output current versus input voltage 1000 10 i c , collector current (ma) t a =75 c 25 c -25 c 100 10 1 100 25 c 75 c 50 010203040 1 0.8 0.6 0.4 0.2 0 v r , reverse bias voltage (volts) c ob , capacitance (pf) figure 17. input voltage versus output current 0 20 40 50 10 1 0.1 0.01 i c , collector current (ma) 25 c 75 c v ce(sat) , maximum collector voltage (volts ) v ce = 10 v f = 1 mhz i e = 0 v t a = 25 c v o = 5 v v o = 0.2 v i c /i b = 10 t a =-25 c t a =-25 c
dtc114eet1 series http://onsemi.com 8 typical electrical characteristics dtc114yet1 10 1 0.1 01020304050 100 10 1 0246810 4 3.5 3 2.5 2 1.5 1 0.5 0 02468101520253035404550 v r , reverse bias voltage (volts) v in , input voltage (volts) i c , collector current (ma) h fe , dc current gain (normalized) figure 18. v ce(sat) versus i c i c , collector current (ma) 020406080 v ce(sat) , maximum collector voltage (volts) figure 19. dc current gain 1 10 100 i c , collector current (ma) figure 20. output capacitance figure 21. output current versus input voltage v in , input voltage (volts) c ob , capacitance (pf) figure 22. input voltage versus output current i c , collector current (ma) 1 0.1 0.01 0.001 -25 c 25 c t a =75 c v ce = 10 300 250 200 150 100 50 0 2468 1520405060708090 f = 1 mhz l e = 0 v t a = 25 c 25 c i c /i b = 10 t a =-25 c t a =75 c 25 c -25 c v o = 0.2 v t a =-25 c 75 c v o = 5 v 25 c 75 c
dtc114eet1 series http://onsemi.com 9 typical applications for npn brts load +12 v figure 23. level shifter: connects 12 or 24 volt circuits to logic in out v cc isolated load from m p or other logic +12 v figure 24. open collector inverter: inverts the input signal figure 25. inexpensive, unregulated current source
dtc114eet1 series http://onsemi.com 10 1.4 1 0.5 min. (3x) 0.5 min. (3x) typical 0.5 soldering pattern unit: mm p d = t j(max) t a r q ja p d = 150 c 25 c 833 c/w = 150 milliwatts ? the soldering temperature and time should not exceed 260 c for more than 10 seconds. ? when shifting from preheating to soldering, the maximum temperature gradient should be 5 c or less. ? after soldering has been completed, the device should be allowed to cool naturally for at least three minutes. gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. ? mechanical stress or shock should not be applied dur- ing cooling * soldering a device without preheating can cause exces- sive thermal shock and stress which can result in damage to the device. information for using the sot416 surface mount package minimum recommended footprint for surface mounted applications surface mount board layout is a critical portion of the total design. the footprint for the semiconductor packages must be the correct size to insure proper solder connection sot416/sc90 power dissipation the power dissipation of the sot416/sc90 is a func- tion of the pad size. this can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. power dissipation for a surface mount device is determined by t j(max) , the maximum rated junction tem- perature of the die, r q ja , the thermal resistance from the device junction to ambient; and the operating temperature, t a . using the values provided on the data sheet, p d can be calculated as follows. the values for the equation are found in the maximum ratings table on the data sheet. substituting these values into the equation for an ambient temperature t a of 25 c, one can calculate the power dissipation of the device which in this case is 125 milliwatts. the 833 c/w assumes the use of the recommended foot- print on a glass epoxy printed circuit board to achieve a power dissipation of 150 milliwatts. another alternative would be to use a ceramic substrate or an aluminum core board such as thermal clad ? . using a board material such as thermal clad, a higher power dissipation can be achieved using the same footprint. interface between the board and the package. with the correct pad geometry, the packages will self align when subjected to a solder reflow process. soldering precautions the melting temperature of solder is higher than the rated temperature of the device. when the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. ? always preheat the device. ? the delta temperature between the preheat and soldering should be 100 c or less.* ? when preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. when using infrared heating with the reflow soldering method, the difference should be a maximum of 10 c.
dtc114eet1 series http://onsemi.com 11 step 1 preheat zone 1 ramp" step 2 vent soak" step 3 heating zones 2 & 5 ramp" step 4 heating zones 3 & 6 soak" step 5 heating zones 4 & 7 spike" step 6 vent step 7 cooling 200 c 150 c 100 c 50 c time (3 to 7 minutes total) t max solder is liquid for 40 to 80 seconds (depending on mass of assembly) 205 to 219 c peak at solder joint desired curve for low mass assemblies 100 c 150 c 160 c 140 c figure 26. typical solder heating profile desired curve for high mass assemblies 170 c for any given circuit board, there will be a group of control settings that will give the desired heat pattern. the operator must set temperatures for several heating zones, and a figure for belt speed. taken together, these control settings make up a heating aprofileo for that particular circuit board. on machines controlled by a computer, the computer remembers these profiles from one operating session to the next. figure 7 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. this profile will vary among soldering systems but it is a good starting point. factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. this profile shows temperature versus time. solder stencil guidelines prior to placing surface mount components onto a printed circuit board, solder paste must be applied to the pads. a solder stencil is required to screen the optimum amount of solder paste onto the footprint. the stencil is made of brass or stainless steel with a typical thickness of 0.008 inches. the stencil opening size for the surface mounted package should be the same as the pad size on the printed circuit board, i.e., a 1:1 registration. typical solder heating profile the line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. the two profiles are based on a high density and a low density board. the vitronics smd310 convection/infrared reflow soldering system was used to generate this profile. the type of solder used was 62/36/2 tin lead silver with a melting point between 177189 c. when this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. the components on the board are then heated by conduction. the circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
dtc114eet1 series http://onsemi.com 12 package dimensions sc75/sot416 case 46301 issue b dim min max min max inches millimeters a 0.70 0.80 0.028 0.031 b 1.40 1.80 0.055 0.071 c 0.60 0.90 0.024 0.035 d 0.15 0.30 0.006 0.012 g 1.00 bsc 0.039 bsc h --- 0.10 --- 0.004 j 0.10 0.25 0.004 0.010 k 1.45 1.75 0.057 0.069 l 0.10 0.20 0.004 0.008 s 0.50 bsc 0.020 bsc notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. m 0.20 (0.008) b a b s d g 3 pl 0.20 (0.008) a k j l c h 3 2 1 style 1: pin 1. base 2. emitter 3. collector on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. dtc114eet1/d thermal clad is a trademark of the bergquist company. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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